Description

FPGA-based speed controller for a synchronous machine with an internal current control loop based on a predictive current controller is presented. Due to their complex computation schemes, predictive current controllers implemented in a full digital system are characterized by an inevitable delay in calculating and applying the switching states to the inverter. Consequently, their performances are affected and the achieved sampling frequency is limited. These digital control limitations are mainly due to the processing speed versus computational complexity trade-off. To cope with this problem, specific digital hardware technology such as FPGA can be used as an alternative digital solution to ensure fast processing operation and to preserve performances of predictive current controllers in spite of their complex computation schemes. Such performances can be preserved, thanks to the high flexibility and high computation capabilities of FPGAs. In order to illustrate this, an FPGA implementation of a synchronous machine speed controller based on a predictive current controller is presented and fully analyzed in this project

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