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Timing Optimization Through Clock Skew Scheduling
Ivan S Kourtev, Baris Taskin, Eby G Friedman
Livre relié | Anglais
167,95 €
+ 335 points
Format
Description
The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the 'performance-per-power' metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.
Spécifications
Parties prenantes
- Auteur(s) :
- Editeur:
Contenu
- Nombre de pages :
- 266
- Langue:
- Anglais
Caractéristiques
- EAN:
- 9780387710556
- Date de parution :
- 21-11-08
- Format:
- Livre relié
- Format numérique:
- Genaaid
- Dimensions :
- 156 mm x 234 mm
- Poids :
- 576 g
