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Systemverilog Assertions and Functional Coverage
Guide to Language, Methodology and Applications
Ashok B Mehta
Livre relié | Anglais
153,95 €
+ 307 points
Format
Description
This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.
Spécifications
Parties prenantes
- Auteur(s) :
- Editeur:
Contenu
- Nombre de pages :
- 356
- Langue:
- Anglais
Caractéristiques
- EAN:
- 9781461473237
- Date de parution :
- 06-08-13
- Format:
- Livre relié
- Format numérique:
- Genaaid
- Dimensions :
- 156 mm x 234 mm
- Poids :
- 721 g
