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SATH: Simulated Annealing C code To FPGA Hardware compiler
Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
Jonathan Phillips
Livre broché | Anglais
58,45 €
+ 116 points
Description
A tool flow is presented for deriving accelerator
circuits on an FPGA
from ANSI C source code by exploring architecture
solutions that
conform to a preset template through scheduling and
mapping
algorithms. A case study carried out on simulated
annealing-based
scheduling software used for spacecraft systems is
explained. The goal
of the tool is the derivation of a design that
maximizes throughput
while minimizing footprint. Results obtained are
compared with a peer
C to RTL tool, a space-borne embedded processor and a
commodity
desktop processor for a variety of problems.
circuits on an FPGA
from ANSI C source code by exploring architecture
solutions that
conform to a preset template through scheduling and
mapping
algorithms. A case study carried out on simulated
annealing-based
scheduling software used for spacecraft systems is
explained. The goal
of the tool is the derivation of a design that
maximizes throughput
while minimizing footprint. Results obtained are
compared with a peer
C to RTL tool, a space-borne embedded processor and a
commodity
desktop processor for a variety of problems.
Spécifications
Parties prenantes
- Auteur(s) :
- Editeur:
Contenu
- Nombre de pages :
- 132
- Langue:
- Anglais
Caractéristiques
- EAN:
- 9783639165128
- Format:
- Livre broché
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